The present invention relates to a method for fabricating a semiconductor structure useful for fabricating a non-planar heterostructure field effect transistor. More specifically, the present invention relates to a method for fabricating a semiconductor structure useful for fabricating a non-planar nitride-based heterostructure field effect transistor, wherein the non-planar region is fabricated in the group III-nitride material aluminum nitride (AlN) and the semiconductor structure is not damaged by dry etching or wet etching.
The use of group III-nitride substrates has become popular for fabricating a non-planar region in a non-planar heterostructure field effect transistor. A non-planar heterostructure field effect transistor is a field effect transistor comprising several different semiconductor layers of semiconductor material, wherein the top layer has a non-planar region. Typically a gate is then formed in the non-planar region. By forming the gate in the non-planar region, the parasitic resistance of the heterostructure field effect transistor is lowered. Furthermore, a higher breakdown voltage and transconductance, as discussed below, can be achieved. However, fabricating a non-planar heterostructure field effect transistor using group III-nitride substrates can be troublesome.
Transconductance is a measure of how the output current of the device changes with the applied voltage at the input of the device. The breakdown voltage is a threshold voltage, which, when exceeded, causes current in the gate to flow uncontrollably. This ultimately leads to the destruction of the device. The breakdown voltage is directly related to the bandgap as described above. Another benefit of having a higher breakdown voltage is improved gate modulation of the channel under a strong RF input drive, which improves power performance of the transistor.
The use of group III-nitride substrates to fabricate a non-planar region in the top layer is popular because group III-nitride substrates have much higher bandgaps than more traditional substrates such as silicon. The bandgap of a substrate refers to the degree to which it can support an applied electric field before breaking down. Thus, the applied voltage that a substrate can maintain is directly proportional to the bandgap of the substrate.
Previous attempts have been made to fabricate a non-planar heterostructure field effect transistor with a top layer comprising GaN, a group III-nitride substrate. However, using GaN has presented problems. When using a wet-etch there is no reliable or controllable method for controlling the regions in the GaN which are being etched. As a result, if the GaN layer is overetched, the layers beneath the GaN layer would be damaged by the wet etchant. There have also been attempts at fabricating a non-planar region in AlGaN where the AlGaN layer was partially wet-etched. Like GaN, using a wet-etch with AlGaN presented problems with controlling the area being etched and the depth of the etched area.
Dry etching processes have also been used in an attempt to create a non-planar region in a GaN substrate. However, dry etching introduces unrecoverable damage to the surface of the GaN substrate. Similar damage is also present when using an AlGaN substrate. The surface damage can be repaired by a post-annealing process, but removing all the surface damage is not possible. Another problem with dry-etching in GaN and AlGaN is the difficulty in controlling the etch depth. Techniques attempting to fabricate recessed gates using GaN are discussed in J. W. Burm et al., xe2x80x9cRecessed gate GaN MODFETS,xe2x80x9d Solid-State Electronics vol 41, pp. 247-250 (1997), and T. Egawa et al., xe2x80x9cRecessed gate AlGaN/GaN MODFET on Sapphire grown by MOCVD,xe2x80x9d IEDM tech Digest, pp. 401-404 (1999). These references both use dry-etching techniques to fabricate the recessed gate.
Therefore, there is a need for a method for fabricating a non-planar heterostructure field effect transistor, wherein the non-planar region is fabricated in a group III-nitride material. There is also a need for a non-planar heterostructure field effect transistor in which dry-etching and wet-etching techniques can be used to create the non-planar region which does not induce damage to the transistor and allows good control of the etching depth.
The present invention provides a transistor having a device structure that allows for the use of dry-etching and wet-etching to create a non-planar region without damaging the transistor. The present invention makes use of the group III-nitride material AlN for creating a non-planar region. AlN has not been used for this application because of the focus on GaN. Because GaN has one of the highest bandgaps of any group III-nitride material, it has been more desirable to find a compatible wet etching process that will work with GaN, than it is to attempt the process with a different group III-nitride material. However, when AlN along with the device structure of the transistor disclosed herein, is processed in conjunction with the wet-etching and dry-etching process disclosed herein, a non-planar region can be fabricated consistently and repeatedly without inducing damage to the rest of the transistor. Such results have not been attainable using GaN or other group III-nitride materials to fabricate non-planar regions in heterostructure field effect transistors.
It is an object of the present invention to provide a novel method for fabricating a non-planar nitride-based heterostructure field effect transistor. The present invention provides a substrate, whereon at least one layer of semiconductor material is deposited. A layer of AlN is deposited on the at least one layer. An active channel is created at the interface of the AlN layer and the at least one layer. Charges are induced in the channel by both spontaneous polarization and piezoelectric strain at the interface. Furthermore, the at least one layer may further consist of a plurality of layers of different semiconductor material. The interface created by the plurality of layers of semiconductor material serves as the channel of the transistor.
After depositing the AlN layer, a capping layer is preferably deposited on the AlN layer. The capping layer helps prevents oxidation from forming on the AlN layer. Ohmic metal contacts are deposited on the capping layer by metal evaporation. The ohmic metal contacts are then annealed so that they diffuse into the transistor, where they contact the channel. The ohmic metal contacts may then be used as a source and drain for the transistor.
Next, a portion of the capping layer is removed using a reactive ion etch (a dry etch) to expose a portion of the AlN layer. However, the exposed portion of the AlN layer is not removed by the dry-etch, thereby acting as an etch stop and preventing damage to the layers of semiconductor material beneath the AlN layer caused by the dry-etch. Then, by using the remaining portion of the capping layer as a mask, a portion of the AlN layer is removed with a solvent to create a non-planar region. The solvent can remove the desired portion of the AlN layer with predictable and repeatable results without reducing the performance of the transistor caused by damage to the AlN layer. Using the solvent to etch the AlN layer helps remove any surface damage on the AlN layer induced by the reaction ion etch. Also, the layers of semiconductor material beneath the AlN layer are insoluble in the solvent. As a result, the layers of semiconductor material work as a controllable etch stop for etching AlN, thereby preventing damage to the semiconductor layers beneath the AlN layer.